1. Design has three blocks Proc (in UT level), connected to Bus (in BCASH level)
   connected to Memory (in BCA level).
   
         ___________        ___________        ___________
        |           |      |           |      |           |
        |           |      |           |      |           |
        | PROCESSOR |------|    BUS    |------|   MEMORY  |
        |           |      |           |      |           |
        |___________|      |___________|      |___________|

2. Processor block is connected to Bus block via SC_INDEXED protocol and Memory block
   is connected to Bus block via user defined MemHndshk protocol.
   
3. The user defined memory hand shake protocol is defined using SC_PROTOCOL 
   construct, to include outmaster-inslave, inmaster-outslave and inoutmaster-
   inoutslave. Only inoutmaster-inoutslave protocol is used in this design.

4. The terminal definition of a inoutmaster memory hand shake protocol includes,
   terminal inout type for data, out type for address, boolean out type for 
   request and RnW signal and in type for acknowledge. 
   
   The memory handshake user defined protocol is defined as

   template <class A,class T>
   SC_PROTOCOL(MemHndshk) {
      ....
      
      SC_INOUTMASTER_P {
         sc_terminal_inout<T,TT_DATA> data;
         sc_terminal_out<A,TT_ADDRESS> addr;
         sc_terminal_out<bool,TT_CONTROL> req;
         sc_terminal_in<bool,TT_CONTROL> ack;
         sc_terminal_out<bool,TT_CONTROL> RnW;
      };
      
      ...
      
      SC_INOUTSLAVE_P {
         sc_terminal_inout<T,TT_DATA> data;
         sc_terminal_in<A,TT_ADDRESS> addr;
         sc_terminal_in<bool,TT_CONTROL> req;
         sc_terminal_out<bool,TT_CONTROL> ack;
         sc_terminal_in<bool,TT_CONTROL> RnW;
         
      ...
      
      };
   };
   
5. Terminals between processor & bus and bus & memory are linked using sc_link_mp.

   sc_link_mp<int> proc_to_bus;
   sc_link_mp<int> mem_to_bus;

6. Instance with terminal link is created as

   Bus_BCASH<int,int> BUS("BUS"); 
   BUS.proc_port(proc_to_bus);
   BUS.mem_port(mem_to_bus);
   ....
    
8. The user defined protocol is used in Bus block as 

   template <class A,class T>
   SC_MODULE(Bus_BCASH){
      sc_inoutslave<T,sc_indexed<T,mem_length> > proc_port;
      sc_inoutmaster<T,MemHndshk<A,T> > mem_port;
      ....
   }   
   
9. Port signals are accessed in the user defined protocol as 
      ...
      if (!proc_port.input()) {
         // reading
         mem_port.RnW = true ;
         mem_port.req = true ;
         SC_WAIT_UNTIL( mem_port.ack == true ) ;
         mem_port.req = false ;
         proc_port = mem_port.data;
      } else { // writing
        ...
      }
