1. Design supports UT level blocks.

2. Design has two parent blocks X1 and Y1.

3. Each parent blocks has two child blocks, X1 has A1 and B1, and Y1 has C1 and
   D1.

                X1                                      Y1
   _____________________________          _____________________________
  |   ______         ______     |        |     ______         ______   |
  |  |      |       |      |    |        |    |      |       |      |  |
  |  |  A1  |p1---p2|  B1  |p3--|p4----p5|--p6|  C1  |p7---p8|  D1  |  |  
  |  |______|       |______|    |        |    |______|       |______|  |
  |_____________________________|        |_____________________________|

4. Clock is used to trigger the autonomous thread in block A1. clock is 
   connected to the parent block X1 and to the child block A1.
   
5. The instanciation of the child blocks are done in parent blocks and 
   connectivity for the child module ports are done in the constructor of the 
   parent modules.
   