// Wait on OR'ed events with timeout reset

#include "systemc.h"

SC_MODULE(intf) {
   
   // Refinable ports
   sc_inslave<int > inp2;
   sc_outmaster<int > outp2;
   
   sc_event input_event1;
   sc_event input_event2;
   sc_event input_event3;
   
   sc_in_clk clk;
   
   int temp1, temp2;
   int data, prev;
   
   // Slave process to determine the data change & generate an event.
   void inter_f0() {
      data = inp2; // Reads in the data from master
      
      // Check Data change, if so generate event
      if (prev != data){
	prev = data;
	sc_time nt(0, sc_ns);
	input_event1.notify(nt);
	cout << " inter_f0: data events notified" << endl;
      }
      wait(); // Static sensitivity wait
   }

   // Clock sensitve process waits to obtain an event notification & transfers data 
   void inter_f1() {
      while(true){
	 cout << " inter_f1: before wait :  " << sc_time_stamp() << endl;
         
         // wait on OR'ed events with in 2 milli sec time out reset
         wait(2,sc_ms,input_event1| input_event2 |input_event3);
         
         cout << " inter_f1: after wait :  " << sc_time_stamp() << endl;
         
         temp1 = inp2; // Reads in the data from master
         outp2 = temp1; // Writes the value to slave
         
         cout << " inter_f1:input, inp2 = " << temp1 << endl;
      }
   }
   
   //Constructor to create & initialize an instance & data structures.
   SC_CTOR(intf) {
      SC_SLAVE(inter_f0, inp2); // Slave thread sensitive to input & create events 
      SC_THREAD(inter_f1); // Clock sensitive thread
      sensitive_pos << clk;
      temp1 = 0;
      temp2 = 0;
      prev = data = 0;
      cout << endl << " intf ctor : initializing ....." << endl << endl;
   }
};
   
