Purpose to trace variables and signals of a Bus port

Design has two blocks, Master_bca and Slave_bca, connected by Fullhandshake 
protocol using outmaster-inslave ports. Data sent from the master block is 
traced using a int variable and acknowledge signal is traced using an bool type 
signal. Data received in the slave block is traced using int variable, bus 
request using an bool signal and bus data using an integer signal.

		    _____________              _____________
		   |              |           |             |
  		   |  Master_bca  |---------->|  Slave_bca  |
 		   |              |           |             |
 		    ------^-------             -----^-------    
 		          |                         |
                          |                         |
   _____________          |-------------------------
  |		|         |
  |  Reset_bca  |---------		    
  |             |
   -------------


All the variables and signals traced are stored in trace2.vcd 
file. The waveforms of this file can be viewed using any vcd 
waveform viewer.

For example, in case of a gtkwave viewer,
Type

	gtkwave trace2.vcd

and select the variables and signals to be displayed using Search, search 
hierarchy/search tree selection. To see the trace as a function of time,
click on the zoom box.

For tracing of terminals of refined bus-ports see the command in the
top_bca.cpp. The blocks must be instantiated, and the ports connected to the
signals prior to tracing. The signal connected to a port at any level of
hierarchy can be traced

	e.g. inst1.inst2.inst3.dat2->req


Also, notice that in the top block, sc_initialize() is followed by creation
of trace file, specification signals to trace, and after sc_start() you must
close the trace file.
